From physics,
step by step toward your own chip.

Planar MOS → FinFET → GAA nanosheets: gates surround more channel surfaces to improve short-channel control. TSMC reports N2 production in Q4 2025; Intel launched 18A-based Core Ultra Series 3 in 2026.

Short channels let the drain disturb switching and increase source-drain tunneling. At about 300 K, an ideal thermionic MOS has a roughly 60 mV/dec subthreshold limit; this is not a universal law for every switching device.

GAA improves control but does not remove thermal statistics or quantum effects. Thin channels introduce contact, mobility, and variation problems; lower voltage can reduce speed and noise margins.

EUV uses 13.5 nm light; High-NA raises numerical aperture from 0.33 to 0.55. “2nm” is neither the exposure wavelength nor the dimension of every feature.

At small features, photon and chemical randomness cause roughness, missing holes, or bridges. Higher NA reduces depth of focus; thin resist, pattern transfer, and overlay must also work.

More exposure dose can reduce some statistical noise but lowers throughput and increases cost. Better optics alone do not solve resist chemistry or defects.

Film and etch engineering control extremely thin structures; research explores 2D semiconductors and more complex stacks.

When a layer is only a few atoms thick, a fixed thickness error becomes a larger relative change. Traps, contamination, contact resistance, and wafer uniformity may limit a product before ideal material properties do.

An excellent small-area sample is not automatically compatible with low-temperature, low-defect, large-area integration or the rest of the process.

Backside power separates supply routing from front-side signals. Intel 18A PowerVia is in products; cells, interconnects, and packages increasingly require joint optimization.

Thinner wires face smaller cross-sections and interface-scattering effects, increasing resistance. RC delay, electromigration, and hotspots grow; density without proportional voltage scaling worsens heat flux.

Backside power frees routing but complicates integration. 3D stacking shortens links but can impede cooling. The formula describes dynamic power only; leakage and I/O power remain.

Caches, HBM, and chiplets place compute and memory closer together. 3DFabric supports multi-die systems through different links and packaging approaches.

Compute throughput can outgrow memory bandwidth; data movement needs energy, pins, and routing. Capacity, bandwidth, latency, and reliability do not scale automatically with logic.

Closer stacks can reduce communication costs but increase heat and assembly pressure. Larger caches consume area, and more bandwidth raises system cost; packaging benefits are not free.

3D NAND increases capacity vertically, beyond planar linewidth scaling. SK hynix describes high-aspect-ratio etch, stress, and cell-current degradation.

More layers complicate deep-hole profiles, dielectric integrity, stress, and cell current, affecting yield and lifetime. DRAM and HBM face distinct capacitor, refresh, stacking, and test constraints.

More layers add process steps and cost. Split stacks and new structures or materials create new connection and uniformity requirements; logic-node roadmaps do not describe memory scaling.

Coverage, formal verification, inline metrology, failure analysis, known-good-die screening, and reliability testing jointly reduce tape-out and shipment risk.

Larger dies encounter more random defects. State spaces, process variation, and multi-die assembly compound risk; simulation cannot prove real silicon under every temperature and lifetime condition.

Stricter screening costs time and money and can still miss failures. Chiplets may improve die yield but add interconnect and assembly failure points. The formula is a simplified random-defect model.

Mature processes, IP reuse, shared shuttles, chiplets, and co-optimization offer different cost-performance paths rather than requiring the smallest node.

Masks, tools, R&D, ramp-up, depreciation, utilities, testing, and inventory must be supported by shipped products. Insufficient volume or yield can erase the business case for a more advanced process.

Customers do not always pay for more functionality. Analog, RF, power, and specialty products often prioritize voltage, noise, reliability, and cost; they are not simply outdated advanced logic.

CFET vertically stacks complementary devices. 2D materials, tunneling devices, monolithic 3D, and alternative architectures explore different density or efficiency gains.

Removing one constraint often exposes another: contacts, thermal budget, defects, drive current, cooling, wiring, programmability, and test can become the next barrier.

Device demonstrations, pilot lines, risk production, volume production, and profitable delivery are different milestones. A roadmap date is not a procurement guarantee; low switching energy is not whole-system efficiency.